1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to such a device having a plurality of semiconductor chips which are stacked over a wiring substrate. The present invention may also relate to a method of manufacturing such a device.
2. Background
Japanese Laid-Open Patent Publication No. 2008-198909 discloses an MCP (Multi-chip package) in which multiple memory chips are stacked on a wiring substrate to offer a large memory capacity and, particularly, discloses a configuration in which an upper memory chip is stacked over a lower memory chip via a resin layer such that wires from the lower memory chip are embedded in the resin layer. Common electrode pads of the upper memory chip and the same of the lower memory chip are connected in common to common connection pads of the wiring substrate via wires.
In addition to the common electrode pads, such a memory chip also includes an independent electrode pad, such as CS (Chip Select) electrode pad, that is electrically connected not to the common connection pad but to an independent connection pad of the wiring substrate by one-to-one coupling.
Japanese Laid-Open Patent Publication No. 2012-054496 discloses an MCP configuration in which multiple semiconductor chips having common electrode pads that can be connected in common to common connection pads and independent electrode pads that cannot be connected in common to the common connection pads are stacked such that each of upper and lower semiconductor chips has a relay pad between the independent electrode pad and the common electrode pads and that the independent electrode pad of the upper semiconductor chip is electrically connected to a connection pad of a wiring substrate via the relay pad of the lower semiconductor chip.
An analysis made by the inventor of the present invention has led to the following conclusion.
The independent electrode pad carried by the upper semiconductor chip and the independent electrode pad carried by the lower semiconductor chip must be electrically connected respectively to independent connection pads different from each other on the wiring substrate. When wire bonding is performed, this process is referred to as “selective wire connection”.
A number of common electrode pads carried by the upper semiconductor chip and a number of common electrode pads carried by the lower semiconductor chip are electrically connected to the same common connection pads on the wiring substrate such that each pair of common electrode pads carried by the upper and lower semiconductor chips are connected to each common connection pad.
In general, in a row of electrode pad group, an independent electrode pad is located closer to the center of the chip as a number of common electrode pads are arranged on both sides of the independent electrode pad (i.e., located closer to the chip edge). The electrode pad group of the semiconductor chip is formed by a process with high precision, but the connection pad group of the wiring substrate is formed by a process with low precision. As a result, the intervals between the connection pads of the wiring substrate turn out to be wider than the intervals between the electrode pads of the semiconductor chip. In addition, to perform selective wire connection, two independent connection pads need to be provided. For these reasons, a row of connection pad group becomes larger in length than a row of electrode pad group.
As a result, an electrode pad located on an end of the electrode pad group is electrically connected to a connection pad more distant from the electrode pad via a wire, which results in an increase in a wire stretching angle. An increase in the wire stretching angle leads to an increase in the length of a wire made of such an expensive material as gold.
The larger wire stretching angle is apt to cause the wire to interfere with the edge of the semiconductor chip, thus affecting the reliability of the semiconductor device. For example, on the wiring substrate, if the connection pads are located distant from the edge of the semiconductor chip, an increase in the wire stretching angle is suppressed. This, however, invites an increase in the wire length and in the substrate size as well, thus leading to an increase in the size of the semiconductor device. A greater unit substrate size results in fewer unit substrates extracted from one wiring substrate, thus leading to higher manufacturing costs.